Impedance-Controlled PCB Design for USB, Ethernet and RF
Fabricator-agreed stackups, field-solver widths, differential pairs and length matching
Impedance-controlled PCB design sets trace width, spacing and stackup so high-speed and RF signals see a defined characteristic impedance, such as 90-ohm USB pairs or 50-ohm RF lines. Electuni designs these boards in Altium Designer with the stackup agreed with the fabricator, for teams whose interfaces fail when impedance is left to chance.
Design → Prototype → Production
Key Facts: Impedance-Controlled PCB Design
- Interfaces
- USB, Ethernet, LVDS, MIPI
- Single-Ended
- 50 Ω RF Lines
- Differential
- 90 Ω / 100 Ω Pairs
- Calculation
- Field Solver
- Verification
- Fabricator Test Coupons
- Lead Designer
- IPC CID+ Certified
What You Get
- Stackup agreed with the fabricator, with materials and dielectric thicknesses
- Impedance table: target, tolerance, layer, width and spacing for each net class
- Differential pair and length-matching rules set up in Altium Designer
- Routed layout with continuous reference planes under controlled traces
- Fabrication notes specifying controlled impedance and test coupons
- Review of return paths, layer transitions and connector breakouts
How We Approach Impedance-Controlled PCB Design
Controlled impedance starts with the stackup, and the stackup belongs to the fabricator. Their actual prepreg and core thicknesses, copper weights and dielectric constants set the trace geometry, so the stackup is requested from or confirmed with the chosen fabricator before routing. Widths and spacings are then calculated with a field solver for each target: single-ended 50-ohm RF lines, 90-ohm differential USB, and 100-ohm differential Ethernet, LVDS and MIPI-class pairs.
The calculated geometry is built into Altium Designer as net classes and design rules, so differential pairs route as coupled pairs with the correct width and gap on each layer. Every controlled trace has a continuous reference plane beneath it, because routing over a split or a plane gap breaks the return path and the impedance with it. Where a pair changes layers, ground return vias are placed beside the signal vias so return current can follow the signal.
Length matching is applied where the interface needs it: tight intra-pair matching for differential pairs, and pair-to-pair matching where the interface specification calls for it. The fabrication notes then state which layers are impedance-controlled, the targets and tolerance, and request test coupons. That lets the fabricator adjust etch widths to hit the targets and verify them by TDR measurement before the boards ship.
Technical Constraints and Trade-offs
- Impedance depends on dielectric thickness, dielectric constant, copper thickness and solder mask, so a width calculated for one fabricator's stackup can be wrong for another's.
- Fabricators commonly offer around plus or minus 10 percent impedance tolerance as standard. Tighter tolerance usually costs more and is not offered everywhere.
- Thin dielectrics give narrow traces for a given impedance, which helps density but pushes geometry toward the fabricator's minimum line width.
- A split or gap in the reference plane under a controlled trace breaks the return path and causes reflections and radiated emissions.
- Connectors, ESD protection parts and large component pads are impedance discontinuities, so their breakouts are kept short and the plane may be voided under large pads to compensate.
- The dielectric constant of FR-4 varies with frequency and resin content, which matters more as signal frequencies rise toward RF bands.
Fabrication and Assembly Handoff
- Stackup drawing with layer order, materials, and dielectric and copper thicknesses
- Impedance table listing each target, tolerance, layer, reference plane and nominal geometry
- Note permitting the fabricator to adjust trace widths to meet impedance, within stated limits
- Request for impedance test coupons and a measurement report
- Gerber or ODB++ data, NC drill files and an IPC-D-356 netlist
From a real project
Custom 24 GHz radar module with an Infineon BGT24 transceiver
A compact circular radar sensor module built around an Infineon BGT24-series 24 GHz radar transceiver, with an STM32 microcontroller for signal processing and control. The multi-layer board integrates the complete RF front-end with dual SMA connectors for the TX and RX antennas, and uses controlled impedance traces, extensive ground stitching vias and shielded component placement. I2C and analog IF outputs (IFI/IFQ) connect it to a larger embedded system.
Read the project on our PCB division's site (opens in a new tab)How an Electuni Engagement Works
Step 1
Discovery
Requirements analysis and feasibility study.
Step 2
Architecture
System design, component selection, and risk assessment.
Step 3
Design
Schematic, layout, firmware, and mechanical CAD.
Step 4
Review
DFM/DFT checks and design review with stakeholders.
Step 5
Prototype
Board fabrication, assembly, and firmware bring-up.
Step 6
Handoff
Production files, BOM, and full documentation package.
Tools & Technologies
- Altium Designer
- Altium Layer Stack Manager
- Altium xSignals
- Saturn PCB Toolkit
- Altium Draftsman
Impedance-Controlled PCB Design FAQ
What is controlled impedance on a PCB?
Controlled impedance means a trace is designed to have a specific characteristic impedance, such as 50 ohms, set by its width, its distance to the reference plane, the dielectric material and nearby copper. Matching the trace to the driver, receiver and cable impedance prevents reflections that distort fast edges and RF signals, and the fabricator is asked to hold it within a tolerance.
Which interfaces need impedance control?
Any signal whose trace length is a significant fraction of its edge or wavelength. Common examples are USB 2.0 and faster (90-ohm differential), Ethernet (100-ohm differential), LVDS, MIPI and HDMI pairs, DDR memory, and RF feed lines at 50 ohms. Slow GPIO, I2C and most SPI buses do not need impedance control on typical board sizes.
Why must the stackup come from the fabricator?
Impedance depends on real material thicknesses and dielectric constants, which differ between fabricators and laminate brands. A width calculated from a generic stackup may land outside tolerance on the board you receive. Agreeing the stackup first, or using the fabricator's published controlled-impedance stackup, means the calculated geometry matches what is actually built and tested.
What is an impedance test coupon?
A test coupon is a strip of traces built on the same production panel as your boards, using the same layers and geometry as the controlled nets. The fabricator measures it with time-domain reflectometry (TDR) to confirm the impedance targets were met, without probing the product boards. The results can be supplied as a report with the shipment.
Does length matching matter for USB 2.0 or Ethernet?
Intra-pair matching matters most: the two traces of a differential pair should be closely matched so the signal stays differential and does not convert to common-mode noise. Pair-to-pair matching across Ethernet pairs is relaxed, because the PHY tolerates skew between pairs. Interfaces such as MIPI or DDR have tighter requirements, which come from the device datasheet.
Can controlled impedance work on a two-layer board?
It can, but it is awkward. On a standard 1.6 mm two-layer board the reference plane is far from the trace, so a 50-ohm microstrip is several millimetres wide. Grounded coplanar waveguide reduces that width, which is why it is common on two-layer RF boards. For USB or Ethernet pairs, a four-layer board with a thin dielectric to the plane is usually simpler.